1. Field of the Invention
The present invention generally relates to the field of current steering switch circuits for high speed and high resolution Digital/Analog conversion.
2. Background Art
Current steering switch circuits, are widely used in high speed Nyquist Digital/Analog converters (DACs). Noises or glitches arise at the switch circuit output during switching actions. The noises or glitches are due in part to feed-through of the switching input signal to the output, across the parasitic capacitance that exists between the input and output nodes. The noises and glitches are also due to unbalanced currents that are injected to the differential output nodes from the bouncing common emitter node of the switching differential pair.
The former is known in the art as type-I switching noise and the latter type-II switching noise. The DAC output noise arising from the switching action is linear if the DAC is fully segmented, where the DAC output signal level is proportional to: the total number of differential pairs that switch their unary tail currents to the positive side of the DAC differential output, minus the number of those that switch to the negative side.
However, for 10-bit or higher resolutions, a segmented DAC architecture that includes an array of switched unary current sources and an array of switched binary weighted current sources is usually used to suppress the complexity. As a result, the net number of differential pairs that switch their tail currents to the positive side of the DAC differential output is not a linear function of the signal level; and therefore, the switching noise causes nonlinear error at the DAC output even if it is identical in magnitude for each switching action.
As the conversion rate increases, the switching time becomes a considerable portion of each conversion cycle and the switching noises may thus dominate the output nonlinearity and thus limit the conversion rate of high resolution DACs.
For example, in cable modem headend applications, it is desirable to run an array of 12-bit (or higher resolution) DACs at approximately 2.5 Giga-Sample/second (GS/s) to send multiple channel signals in each DAC. The conversion cycle is 400 pico-seconds (ps), while the differential pair switching time in the current bipolar complimentary metal oxide semiconductor (BiCMOS) technology is about 40 ps. Thus, the switching noises could represent as much as one tenth of a DAC output waveform. Simulations illustrate that the switching noises limit the spurious-free dynamic range (SFDR) of the DAC output to below 60 dB.
What is needed, therefore, are techniques to suppress the switching noises to impove the SFDR beyond 60 dB